1. Field of the Invention
The present invention relates generally to digital computers having memory and I/O including dynamic memory and, more particularly, relates to a system for reducing the time required to refresh the dynamic memory.
2. Description of the Prior Art
An important characteristic of dynamic memory is the requirement of periodically refreshing the memory to preserve the data stored. This refreshing operation must take precedence over all other operations or important data will be irretrievably lost.
Generally the transfer of data between a CPU and memory or I/O occurs during a CPU bus cycle initiated by the CPU and controlled by a separate BUS CONTROLLER. Also, a separate timer functions to generate a refresh request signal at specified intervals determined by the refresh requirements of the dynamic memory. In PC type computers, a refresh system requests the bus from the CPU and puts the CPU in a wait state while the refresh operation is completed. In a PC-XT type of computer, the refresh interval is about 15 microseconds. One row of memory is refreshed every refresh interval.
Typical refresh systems utilize a DMA controller so that cycles required for arbitration are utilized in addition to the cycles required to refresh the memory. A standard PC-XT using the standard refresh system consumes about 2.5 microseconds or about 17% of each refresh interval. A PC-AT type computer also extends the time consumed for refresh by requiring extra cycles for arbitration.
Thus, the standard refresh system significantly reduces the usable portion of the CPU cycle time and decreases the effective speed of the computer.